1. Field of the Invention
The present invention relates to a clock generator; and more particularly to a delayed locked loop (DLL) clock generator in double data rate (DDR) synchronous random access memory (SDRAM).
2. Prior Art of the Invention
In general, a module in a semiconductor memory circuit is synchronized with clocks and performs various functions, for example, reading data from a memory cell or writing data to the memory cell. The synchronization is performed in accordance with clock signals generated in a clock generator. In a semiconductor device, a clock signal having a certain period is used in order to compensate skew between a clock signal and a data signal or between two clock signals. More particularly, in DDR SDRAM, when the data signal is outputted in synchronization with a clock, there is a skew due to an input delay of the clock and a data-out path delay. Accordingly, an additional internal clock is used for compensating the skew due to the delay mentioned above.
Referring to FIG. 1, when a data signal is outputted in synchronization with a clock signal clk, a skew td1 occurs. For compensating the skew td1, a new clock signal is used, which refers to a DLL (Delay Locked Loop) clock signal dll_clk. If the data signal is synchronized with the DLL clock signal dll_clk, the data signal is outputted without the skew tdl.
The DLL clock signal dll_clk precedes the clock signal clk by the input delay td1. Substantially, the DLL clock signal dll_clk is generated by delaying the clock signal as much as a subtraction td2 of the input delay td1 from a period tck of the clock signal. That is, a substantial delay value can be expressed by the equation as follows:
td2=tckxe2x88x92td1.
However, a conventional DLL circuit generates an internal clock signal compensating the skew after a considerably long time.
Therefore, an object of the invention is to provide a DLL generator having a shorter locking time.
To obtain the object of the present invention, there is provided an apparatus for generating a delayed locked loop (DLL) clock signal, comprising: a first clock generator for receiving a first clock signal which is an external synchronization clock signal and has a first time period, and for generating a second clock delayed by a first delay time in comparison with the first clock; a second clock generator for generating a first control signal having a pulse width corresponding to a difference between the first time period and the first delay time; and a third clock generator for generating a DLL clock signal which is slower than the first clock signal by the pulse width of the first control signal.
To obtain the object of the present invention, there is provided an apparatus for generating a delayed locked loop (DLL) clock signal, comprising: a pulse generator for generating a pulse signal of which a pulse width corresponds to a predetermined delay time; a first delay chain including a plurality of delay means, for delaying the pulse signal by a predetermined delay time in order; and a second delay chain having the same delay time as the first delay chain, for delaying an external clock signal responsive to an output signal from the delay means.